1. Field of the Invention
The present invention relates to a nonvolatile semiconductor storage device and to a method of manufacturing the same, and more particularly to a charge trap-type nonvolatile semiconductor storage device and to a method of manufacturing the same.
2. Description of Related Art
As the nonvolatile semiconductor storage device, there has been known a charge trap-type nonvolatile semiconductor storage device. For example, JP-A-2004-312009 (corresponding U.S. Pat. No. 7,005,349B2) discloses a method of manufacturing a silicon-oxide-nitride-oxide-silicon (SONOS) memory device.
FIGS. 1 to 9 are cross-sectional views showing the SONOS memory device manufacturing method in JP-A-2004-312009. First, as shown in FIG. 1, a dielectric layer 111 made of ONO (oxide-nitride-oxide) is formed on a semiconductor substrate 110. Then, a first conductive layer 130a is formed on the dielectric layer 111. Thereafter, a buffer layer 180 is formed on the first conductive layer 130a. Then, as shown in FIG. 2, a trench 181 from which a partial surface of the first conductive layer 130a is exposed is formed on the buffer layer 180. Subsequently, as shown in FIG. 3, a first insulating film 117a is so formed as to cover the trench 181.
Then, as shown in FIG. 4, the first insulating film 117a is etched back to form a first insulating spacer 117 on an inner wall of the trench 181. Thereafter, as shown in FIG. 5, an exposed portion of the first conductive layer 130a and a portion of the dielectric layer 111 therebelow are selectively sequentially removed with the first insulating spacer as an etching mask, thereby dividing the first conductive layer 130a and the dielectric layer 111 into two portions, respectively.
Subsequently, as shown in FIG. 6, a gate dielectric layer 115 is formed on the semiconductor substrate 110 exposed by separation of the dielectric layer 111. The gate dielectric layer 115 extends on the first insulating spacer 117 so as to insulate the two first conductive layers 130a from each other so that the two separated first conductive layers 130a below the first insulating spacers 117 are allowed to function as independent gates (control gates 130), respectively. Subsequently, a second conductive layer 120 (word gate 120) embedded in a gap between both side walls of the trench is formed on the gate dielectric layer 115. Then, a capping insulating layer 118 is so formed as to cover the upper portion of the second conductive layer 120.
Then, as shown in FIG. 7, the buffer layer 180 is removed with the first insulating spacer 117 as an etching mask. Subsequently, as shown in FIG. 8, a portion of the first conductive layer 130a which has been exposed by removal of the buffer layer 180, and a portion of the dielectric layer 111 therebelow are selectively sequentially removed with the first insulating spacer 117 as an etching mask to provide the dielectric layer 111 and the first conductive layer 130 (control gate 130) which have been divided into two parts, respectively, as a final pattern.
Then, as shown in FIG. 9, a first diffusion layer 151a is formed on the semiconductor substrate 110 exposed outside of the final pattern (dielectric layer 111) by ion implantation. Then, a second insulating spacer 116 is formed on the side walls of the dielectric layer 111 and the first conductive layer 130 which are the final pattern. Then, a second diffusion layer 151b is formed on the semiconductor substrate 110 by ion implantation with the second insulating spacer 116 as a mask. Thereafter, although being not shown, a second silicide layer is selectively formed on the second diffusion layer 151b, and a third silicide layer is formed on the second conductive layer 120 in a silicide inducing process. The first conductive layer and the second conductive layer are each formed to include a conductive silicon layer.
Also, T. Saito et al., “Hot hole erase characteristics and reliability in twin MONOS device”, IEEE non-volatile semiconductor memory workshop, pp. 50-52, 2003 discloses a device of a twin-MONOS structure as a nonvolatile semiconductor memory device of a split gate type.